1. Field of the Invention
This invention relates to the structure and operation of a pre-amplifier for amplifying signals received from a transducer of an electronic measuring system. More particularly, this invention relates to the structure and operation of a fast response, open loop pre-amplifier.
2. Description of Related Art
Electronic measuring systems, such as capacitive or inductive calipers, linear scales and the like, such as those shown in U.S. Pat. Nos. 4,420,754, 4,878,013, 4,879,508 and 5,023,559, and in U.S. patent application Ser. No. 08/441,769 filed May 16, 1995 (now U.S. patent application Ser. No. 08/912,567, filed Aug. 18, 1997), herein incorporated by reference, are well known in the art. As shown in FIG. 1, the prior art measuring system 20 includes a microprocessor controller 22 which controls a ROM 28, an amplifier 40, a demodulator 50, an integrator 52 and an analog-to-digital (A/D) converter 54. An oscillator 26 is connected to the microprocessor controller 22 and a modulator 30. The ROM 28 outputs, for example, 8 bits of data to the modulator 30 based on the control signals received from the microprocessor controller 22.
The modulator 30 modulates the oscillator signal received from the oscillator 26 based on the data received from the ROM 28 and outputs the modulated oscillator signals to the measurement transducer 32.
The measurement transducer 32 can be any known type of electronic transducer, such as a relative position capacitive position encoder, an absolute position capacitive position encoder, a relative position inductive position encoder, an absolute position inductive position encoder, or the like. The modulated signals are input by the transducer 32. The transducer 32 further modulates those signals based on the relative or absolute position between a slide of the transducer and a scale of the transducer. The transducer thus outputs a signal which is indicative of the relative or absolute position of the slide on the scale. This signal is output to the amplifier 40.
The amplifier 40, based on control signals received from the microprocessor controller 22, amplifies the signal received from the transducer 32. The amplified signal is then output to the demodulator 50. The demodulator 50 may include a sample and hold circuit for sampling and holding the amplified signal from the amplifier 40 based on control signals received from the microprocessor controller 22. The demodulator 50 then demodulates the sampled signal based on control signals from the microprocessor controller 22. The demodulator 50 then outputs the demodulated signals to the integrator 52.
The integrator 52 integrates a number of signals received from the demodulator 50 based on control signals received from the microprocessor controller 22. The integrator 52 then outputs the integrated signal to the A/D converter 54. The A/D converter 54 then converts the analog integrated signal received from the integrator 52 to a digital signal based on control signals received from the microprocessor controller 22. The A/D converter 54 then outputs the digital signal to the microprocessor controller 22.
The microprocessor controller 22 then processes the digital signal received from the A/D converter 54 to determine the relative or absolute position of the slider of the transducer 32 to the scale of the transducer 32. The determined relative or absolute position is output to a display 24 to be viewed by an operator. Alternatively, the position signal output by the microprocessor controller 22 can be output to another controller, such as the controller of a numerically controlled machine tool, a computer or the like.
FIG. 2 shows a well known amplifier circuit for the amplifier 40. As shown in FIG. 2, the transducer signal input from the transducer 32 is connected to one plate of a capacitor 42. The other plate of the capacitor 42 is connected to the base of a PMOS transistor 44, the base of a NMOS transducer 46 and one pole of a switch 48. The transistors 44 and 46 are connected in series between a supply voltage V.sub.DD and ground. The output of the amplifier 40, which is connected to the input of the demodulator 50, is connected between the PMOS transistor 44 and the NMOS transistor 46. Furthermore, the other pole of the switch 48 is connected directly to the output of the amplifier 40. Thus, when the switch 48 is closed, the input to the amplifier 40 is connected directly to the output of the amplifier 40, resetting the amplifier 40, as described below.
In operation, when the transducer 32 outputs a voltage signal to the amplifier 40, the NMOS transistor 46 and the PMOS transistor 44 act in concert to amplify the input voltage signal input to the amplifier 40 to obtain the amplified output voltage signal from the amplifier 40. The gain in amplitude of the amplified output voltage signal output by the amplifier 40 is based on the transconductance g.sub.44 and the output conductance c.sub.44 of the PMOS transistor 44 and the transconductance g.sub.46 and the output conductance c.sub.46 of the NMOS transistor 46. In particular, the gain G provided by the amplifier 40 is EQU G=-(g.sub.44 +g.sub.46)/(c.sub.44 +c.sub.46).
The transconductances g.sub.44 and g.sub.46 are a function of the PMOS transconductance parameter K'.sub.P and the NMOS transconductance parameter K'.sub.N, respectively. The output conductances c.sub.44 and c.sub.46 are a function of the PMOS channel length modulation parameter .lambda..sub.P and the NMOS channel length modulation parameter .lambda..sub.N, respectively. Each of these parameters is process dependent, and will vary independently of the each other.
When the switch is closed, the output to the demodulator 50 stabilizes at the midpoint of the curve shown in FIG. 3. When the switch 48 is open, the amplifier 40 provides a very fast, high-gain amplification of the input signal received from the transducer 32.
However, due to the differing manufacturing processes required to form the PMOS transistor 44 and the NMOS transistor 46, the transconductance parameters K'.sub.P and K'.sub.N and the channel length modulation parameters .lambda..sub.P and .lambda..sub.N will vary uncontrollably. Thus, it is extremely difficult to match the transconductance g.sub.44 and the output conductance c.sub.44 of the PMOS transducer 44 and the transconductance g.sub.46 and the output conductance c.sub.46 of the NMOS transistor 46. Thus, the amount of amplification provided by the amplifier 40 will be difficult to predict by design. However, it is necessary for the amplifier to have a controlled, linear and predictable gain. Because the manufacturing processes which are used to form the PMOS transistor 44 and the NMOS transistor 46 are difficult to control, and the processes are different for each of the transistors 44 and 46, a predictable gain is thus impossible to obtain.
The transconductance g of a PMOS or NMOS transistor is a function of the transconductance parameter K', while the output conductance c of a PMOS or NMOS transistor is a function of the channel length modulation parameter .lambda.. However, the transconductance parameter K' and the channel length modulation parameter .lambda. of such MOS transistors can each vary by .+-.30% due to uncontrollable manufacturing process variations. Thus, a predictable transconductance g and a predictable output conductance c for such MOS transistors is difficult to obtain.
FIG. 4 shows another possible amplifier 40'. As shown in FIG. 4, the amplifier 40' is generally similar to the amplifier 40 shown in FIG. 3. However, in the amplifier 40' shown in FIG. 4, the gate of the PMOS transistor 44 is connected to the node between the transistors 44 and 46, rather than to the capacitor 42. In the amplifier 40' shown in FIG. 4, the gain G of the amplifier 40' is: EQU G=(-g.sub.44 /g.sub.46).sup.1/2
where g.sub.44 is the transconductance of the PMOS transducer 44, and g.sub.46 is the transconductance of the NMOS transistor 46. In general, the gain G of the amplifier 40' will also be highly dependent upon the process-dependent transconductance parameters K'.sub.P and K'.sub.N of the transistors 44 and 46, but not upon the channel length modulation parameters .lambda..sub.N and .lambda..sub.P. Therefore, the gain will be more predictable by design than in the previous amplifier 40. In order to achieve some amplification, the transconductance g.sub.46 of the NMOS transistor 46 will be very much larger than the transconductance g.sub.44 of the PMOS transistor 44.
Furthermore, in the amplifiers 40 and 40', the output will generally not be perfectly linear, as seen on the curve shown in FIG. 3. To compensate for this non-linearity, two amplifiers 40.sub.1 ' and 40.sub.2 ' can be combined and connected to the inverting and non-inverting inputs of an operational amplifier, as shown in the amplifier 40" of FIG. 5. In the amplifier 40", the transducer 32 must output two outputs, a positive signal IN+ and a negative signal IN-. Each of the positive and negative signals IN+ and IN- from the transducer 32 are input to one of a pair of capacitors 47. The positive and negative signals IN+ and IN- are then connected to the amplifiers 40.sub.1 ' and 40.sub.2 ', respectively, of the amplifier 40". The output of the first and second amplifiers 40.sub.1 ' and 40.sub.2 ' of the amplifier 40", shown at points A and B, respectively, are equal to: EQU V.sub.A =k(V.sub.IN+ /2+V.sub.CM) EQU V.sub.B =k(V.sub.IN- /2+V.sub.CM)
where V.sub.IN+ is the positive voltage output by the transducer 32, V.sub.IN- is the negative voltage output by the transducer 32, and V.sub.CM is the common mode voltage.
The amplifier 40" shown in FIG. 5 allows the non-linearities of the amplifiers 40.sub.1 ' and 40.sub.2 ' to self-compensate. However, the amplifier 40" introduces the common mode voltage V.sub.CM. The common mode voltage V.sub.CM arises because the positive voltage signal IN+ and the negative voltage signal IN- output by the transducer 32 cannot be fully isolated from each other. This arises due to the geometry of the transducer 32, noise in the electronic measuring system 20, noise picked up from the environment by the transducer 32, and cross-talk between the positive voltage signal IN+ and the negative voltage signal IN- within the transducer 32.
The common mode voltage V.sub.CM is undesirable because margin is lost due to saturation of the transistors. That is, as shown in FIG. 6, when the common mode voltage V.sub.CM is not present, the original margin M.sub.O between the saturation voltage V.sub.S and the input voltage V.sub.IN /2 is significantly larger than the margin M.sub.CM available when the common mode voltage is present.
Furthermore, as shown in FIG. 6, when the common mode voltage V.sub.CM is present, the signals received from the transducer 32 are no longer in the linear operating range O of the amplifier 40". Thus, the common mode voltage V.sub.CM causes the amplifier 40" to lose linearity. Finally, the common mode voltage V.sub.CM can generate other circuit imbalances affecting the linearity and predictability of the gain from the amplifier 40".